DDR5 MRDIMM2 Verification IP

Truechip's DDR5 MRDIMM2 Verification IP provides an effective & efficient way to verify the components interfacing with DDR5 MRDIMM2 interfaces of an ASIC/FPGA or SoC. Truechip's DDR5MRDIMM2 VIP is fully compliant with Standard JEDEC Specifications. This VIP is lightweight with an easy plug-and-play interface so that there isno hit on the design time and the simulation time.

Key Benefits

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
• 24X5 customer support & response under 90 Min.
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity examples for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment

Features

• Compliance with JEDEC DDR5 MRDIMM2 specifications.
• Supports module configurations: 2Rx8, 2Rx4, 4Rx8, 4Rx4.
• Support for high-speed bandwidth (Speeds reach up to 12,800 MT/s) scaling and multiplexed rank operations.
• Available from the size 32GB to 256GB.
• Supports two sub-channels, each divided into 2 pseudo-channels.
• Supported PMIC, TS and SPD HUB.
• Supports 1N and 2N modes
• Supports the SDR1,SDR2 and DDR mode.
• Supports the trainings Supports BCOM Training Mode, Strobe & Data Trainings DCATM, DCSTM, QCATM, QCSTM & Enhanced DCATM.
• Supports Cyclic Redundancy Check (CRC).
• Supports Programmable burst lengths.
• Supports capturing all the valid DDR5 commands including Activate, Read Write, Precharge.
• Supports Power-up Reset and initialization sequences.
• Supports Precharge Power-Down, Active Power-Down, Self-Refresh operation (with and without clock stop).
• Provides the I2c sideband support.
• Reports various timing errors, which can be used to check timing violations.
• Provides full control to the user to enable/disable various types of messages.
• Supports advanced System Verilog features like constrained random testing.
• Supports dynamically configurable modes.
• Strong Protocol Monitor with real time exhaustive programmable checks.
• Supports Dynamic as well as Static Error Injection scenarios.
• On the fly protocol checking using protocol check functions, static and dynamic assertion.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
• Graphical analyzer to show transactions for easy debugging

Deliverables

• DDR5-SDRAMModel, Multiplexed Rank RCD Model &Multiplexed Rank Data Buffer Model
• DDR5 Monitor & Scoreboard
• DDR5 Memory Controller BFM/Agent
• DDR5 PHY BFM model
• DDR5 PHY Monitor and Scoreboard
• DDR5 RCD & Data Buffer Monitor
• Test-Bench Configurations
• Test Suite (Available in Source code)
  • Basic Protocol Tests
  • Directed & Random Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes